Kolloquium

Abstract:

Microelectronics devices (microprocessors, memory chips) have obeyed Moore's Law for several decades – processing power doubles every 2 years. The vast majority of that improvement in processing power has occurred by shrinking the transistors in microprocessors to dimensions that are now less than 5 nm and stacking memory bits to now more than 512 layers. This impressive performance in semiconductor fabrication has been made possible, in large part, by plasma processing. Plasma etching and deposition has enabled high volume manufacturing (HVM) of modern microelectronics by economically adding and removing materials with atomic resolution. This performance in turn results from an impressive mastery of plasma transport, chemistry and plasma surface interactions. As the industry has matured and experimental development has become more expensive, the need for computer modeling has increased to speed the development cycle (with the motivation of reducing cost). The vision of the industry is now to develop a digital twin, a computer representation of the entire HVM process which encompasses nearly 1000 steps to make a microprocessor. In this talk, an update on modeling of reactor and feature scale processes for plasma etching will be provided in the context of the digital twin, and the roles of physics based and machine learning approaches. The requirements and outlook for the digital twin will be discussed.